
face2:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005b0 <_init>:
  4005b0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005b4:	910003fd 	mov	x29, sp
  4005b8:	94000044 	bl	4006c8 <call_weak_fn>
  4005bc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005c0:	d65f03c0 	ret

Disassembly of section .plt:

00000000004005d0 <.plt>:
  4005d0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4005d4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10138>
  4005d8:	f947fe11 	ldr	x17, [x16, #4088]
  4005dc:	913fe210 	add	x16, x16, #0xff8
  4005e0:	d61f0220 	br	x17
  4005e4:	d503201f 	nop
  4005e8:	d503201f 	nop
  4005ec:	d503201f 	nop

00000000004005f0 <exit@plt>:
  4005f0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4005f4:	f9400211 	ldr	x17, [x16]
  4005f8:	91000210 	add	x16, x16, #0x0
  4005fc:	d61f0220 	br	x17

0000000000400600 <_setjmp@plt>:
  400600:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400604:	f9400611 	ldr	x17, [x16, #8]
  400608:	91002210 	add	x16, x16, #0x8
  40060c:	d61f0220 	br	x17

0000000000400610 <malloc@plt>:
  400610:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400614:	f9400a11 	ldr	x17, [x16, #16]
  400618:	91004210 	add	x16, x16, #0x10
  40061c:	d61f0220 	br	x17

0000000000400620 <__libc_start_main@plt>:
  400620:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400624:	f9400e11 	ldr	x17, [x16, #24]
  400628:	91006210 	add	x16, x16, #0x18
  40062c:	d61f0220 	br	x17

0000000000400630 <__gmon_start__@plt>:
  400630:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400634:	f9401211 	ldr	x17, [x16, #32]
  400638:	91008210 	add	x16, x16, #0x20
  40063c:	d61f0220 	br	x17

0000000000400640 <abort@plt>:
  400640:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400644:	f9401611 	ldr	x17, [x16, #40]
  400648:	9100a210 	add	x16, x16, #0x28
  40064c:	d61f0220 	br	x17

0000000000400650 <puts@plt>:
  400650:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400654:	f9401a11 	ldr	x17, [x16, #48]
  400658:	9100c210 	add	x16, x16, #0x30
  40065c:	d61f0220 	br	x17

0000000000400660 <longjmp@plt>:
  400660:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400664:	f9401e11 	ldr	x17, [x16, #56]
  400668:	9100e210 	add	x16, x16, #0x38
  40066c:	d61f0220 	br	x17

0000000000400670 <printf@plt>:
  400670:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400674:	f9402211 	ldr	x17, [x16, #64]
  400678:	91010210 	add	x16, x16, #0x40
  40067c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400680 <_start>:
  400680:	d280001d 	mov	x29, #0x0                   	// #0
  400684:	d280001e 	mov	x30, #0x0                   	// #0
  400688:	aa0003e5 	mov	x5, x0
  40068c:	f94003e1 	ldr	x1, [sp]
  400690:	910023e2 	add	x2, sp, #0x8
  400694:	910003e6 	mov	x6, sp
  400698:	580000c0 	ldr	x0, 4006b0 <_start+0x30>
  40069c:	580000e3 	ldr	x3, 4006b8 <_start+0x38>
  4006a0:	58000104 	ldr	x4, 4006c0 <_start+0x40>
  4006a4:	97ffffdf 	bl	400620 <__libc_start_main@plt>
  4006a8:	97ffffe6 	bl	400640 <abort@plt>
  4006ac:	00000000 	.inst	0x00000000 ; undefined
  4006b0:	00400cfc 	.word	0x00400cfc
  4006b4:	00000000 	.word	0x00000000
  4006b8:	00400d20 	.word	0x00400d20
  4006bc:	00000000 	.word	0x00000000
  4006c0:	00400da0 	.word	0x00400da0
  4006c4:	00000000 	.word	0x00000000

00000000004006c8 <call_weak_fn>:
  4006c8:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10138>
  4006cc:	f947f000 	ldr	x0, [x0, #4064]
  4006d0:	b4000040 	cbz	x0, 4006d8 <call_weak_fn+0x10>
  4006d4:	17ffffd7 	b	400630 <__gmon_start__@plt>
  4006d8:	d65f03c0 	ret
  4006dc:	00000000 	.inst	0x00000000 ; undefined

00000000004006e0 <deregister_tm_clones>:
  4006e0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4006e4:	91016000 	add	x0, x0, #0x58
  4006e8:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  4006ec:	91016021 	add	x1, x1, #0x58
  4006f0:	eb00003f 	cmp	x1, x0
  4006f4:	540000a0 	b.eq	400708 <deregister_tm_clones+0x28>  // b.none
  4006f8:	90000001 	adrp	x1, 400000 <_init-0x5b0>
  4006fc:	f946e021 	ldr	x1, [x1, #3520]
  400700:	b4000041 	cbz	x1, 400708 <deregister_tm_clones+0x28>
  400704:	d61f0020 	br	x1
  400708:	d65f03c0 	ret
  40070c:	d503201f 	nop

0000000000400710 <register_tm_clones>:
  400710:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400714:	91016000 	add	x0, x0, #0x58
  400718:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40071c:	91016021 	add	x1, x1, #0x58
  400720:	cb000021 	sub	x1, x1, x0
  400724:	9343fc21 	asr	x1, x1, #3
  400728:	8b41fc21 	add	x1, x1, x1, lsr #63
  40072c:	9341fc21 	asr	x1, x1, #1
  400730:	b40000a1 	cbz	x1, 400744 <register_tm_clones+0x34>
  400734:	90000002 	adrp	x2, 400000 <_init-0x5b0>
  400738:	f946e442 	ldr	x2, [x2, #3528]
  40073c:	b4000042 	cbz	x2, 400744 <register_tm_clones+0x34>
  400740:	d61f0040 	br	x2
  400744:	d65f03c0 	ret

0000000000400748 <__do_global_dtors_aux>:
  400748:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40074c:	910003fd 	mov	x29, sp
  400750:	f9000bf3 	str	x19, [sp, #16]
  400754:	d0000093 	adrp	x19, 412000 <exit@GLIBC_2.17>
  400758:	39416260 	ldrb	w0, [x19, #88]
  40075c:	35000080 	cbnz	w0, 40076c <__do_global_dtors_aux+0x24>
  400760:	97ffffe0 	bl	4006e0 <deregister_tm_clones>
  400764:	52800020 	mov	w0, #0x1                   	// #1
  400768:	39016260 	strb	w0, [x19, #88]
  40076c:	f9400bf3 	ldr	x19, [sp, #16]
  400770:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400774:	d65f03c0 	ret

0000000000400778 <frame_dummy>:
  400778:	17ffffe6 	b	400710 <register_tm_clones>

000000000040077c <var>:
  40077c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400780:	910003fd 	mov	x29, sp
  400784:	52800c20 	mov	w0, #0x61                  	// #97
  400788:	39007fa0 	strb	w0, [x29, #31]
  40078c:	39407fa0 	ldrb	w0, [x29, #31]
  400790:	b9001ba0 	str	w0, [x29, #24]
  400794:	39407fa1 	ldrb	w1, [x29, #31]
  400798:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  40079c:	91374000 	add	x0, x0, #0xdd0
  4007a0:	2a0103e2 	mov	w2, w1
  4007a4:	b9401ba1 	ldr	w1, [x29, #24]
  4007a8:	97ffffb2 	bl	400670 <printf@plt>
  4007ac:	52800060 	mov	w0, #0x3                   	// #3
  4007b0:	b90017a0 	str	w0, [x29, #20]
  4007b4:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4007b8:	91376000 	add	x0, x0, #0xdd8
  4007bc:	b94017a1 	ldr	w1, [x29, #20]
  4007c0:	97ffffac 	bl	400670 <printf@plt>
  4007c4:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4007c8:	9137a000 	add	x0, x0, #0xde8
  4007cc:	fd400000 	ldr	d0, [x0]
  4007d0:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4007d4:	91378000 	add	x0, x0, #0xde0
  4007d8:	97ffffa6 	bl	400670 <printf@plt>
  4007dc:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4007e0:	9137a000 	add	x0, x0, #0xde8
  4007e4:	fd400000 	ldr	d0, [x0]
  4007e8:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4007ec:	91376000 	add	x0, x0, #0xdd8
  4007f0:	97ffffa0 	bl	400670 <printf@plt>
  4007f4:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4007f8:	91376000 	add	x0, x0, #0xdd8
  4007fc:	52802741 	mov	w1, #0x13a                 	// #314
  400800:	97ffff9c 	bl	400670 <printf@plt>
  400804:	d503201f 	nop
  400808:	a8c27bfd 	ldp	x29, x30, [sp], #32
  40080c:	d65f03c0 	ret

0000000000400810 <jmp>:
  400810:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400814:	910003fd 	mov	x29, sp
  400818:	52800060 	mov	w0, #0x3                   	// #3
  40081c:	b9001fa0 	str	w0, [x29, #28]
  400820:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400824:	91018000 	add	x0, x0, #0x60
  400828:	97ffff76 	bl	400600 <_setjmp@plt>
  40082c:	7100001f 	cmp	w0, #0x0
  400830:	540000e0 	b.eq	40084c <jmp+0x3c>  // b.none
  400834:	b9401fa1 	ldr	w1, [x29, #28]
  400838:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  40083c:	91376000 	add	x0, x0, #0xdd8
  400840:	97ffff8c 	bl	400670 <printf@plt>
  400844:	52800000 	mov	w0, #0x0                   	// #0
  400848:	97ffff6a 	bl	4005f0 <exit@plt>
  40084c:	528000a0 	mov	w0, #0x5                   	// #5
  400850:	b9001fa0 	str	w0, [x29, #28]
  400854:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400858:	91018000 	add	x0, x0, #0x60
  40085c:	52800021 	mov	w1, #0x1                   	// #1
  400860:	97ffff80 	bl	400660 <longjmp@plt>

0000000000400864 <snode>:
  400864:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400868:	910003fd 	mov	x29, sp
  40086c:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400870:	9137c001 	add	x1, x0, #0xdf0
  400874:	910063a0 	add	x0, x29, #0x18
  400878:	f9400022 	ldr	x2, [x1]
  40087c:	f9000002 	str	x2, [x0]
  400880:	b9400821 	ldr	w1, [x1, #8]
  400884:	b9000801 	str	w1, [x0, #8]
  400888:	910063a0 	add	x0, x29, #0x18
  40088c:	f90017a0 	str	x0, [x29, #40]
  400890:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400894:	91376000 	add	x0, x0, #0xdd8
  400898:	d2800181 	mov	x1, #0xc                   	// #12
  40089c:	97ffff75 	bl	400670 <printf@plt>
  4008a0:	f94017a0 	ldr	x0, [x29, #40]
  4008a4:	b9400001 	ldr	w1, [x0]
  4008a8:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4008ac:	91376000 	add	x0, x0, #0xdd8
  4008b0:	97ffff70 	bl	400670 <printf@plt>
  4008b4:	d503201f 	nop
  4008b8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008bc:	d65f03c0 	ret

00000000004008c0 <d>:
  4008c0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4008c4:	910003fd 	mov	x29, sp
  4008c8:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4008cc:	91376000 	add	x0, x0, #0xdd8
  4008d0:	52800021 	mov	w1, #0x1                   	// #1
  4008d4:	97ffff67 	bl	400670 <printf@plt>
  4008d8:	d503201f 	nop
  4008dc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4008e0:	d65f03c0 	ret

00000000004008e4 <foo>:
  4008e4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008e8:	910003fd 	mov	x29, sp
  4008ec:	b9001fa0 	str	w0, [x29, #28]
  4008f0:	b9001ba1 	str	w1, [x29, #24]
  4008f4:	52800020 	mov	w0, #0x1                   	// #1
  4008f8:	b9002fa0 	str	w0, [x29, #44]
  4008fc:	b9401ba0 	ldr	w0, [x29, #24]
  400900:	7100001f 	cmp	w0, #0x0
  400904:	540003ad 	b.le	400978 <foo+0x94>
  400908:	b9401ba0 	ldr	w0, [x29, #24]
  40090c:	7100001f 	cmp	w0, #0x0
  400910:	12000000 	and	w0, w0, #0x1
  400914:	5a80a400 	cneg	w0, w0, lt  // lt = tstop
  400918:	7100041f 	cmp	w0, #0x1
  40091c:	540000a1 	b.ne	400930 <foo+0x4c>  // b.any
  400920:	b9402fa1 	ldr	w1, [x29, #44]
  400924:	b9401fa0 	ldr	w0, [x29, #28]
  400928:	1b007c20 	mul	w0, w1, w0
  40092c:	b9002fa0 	str	w0, [x29, #44]
  400930:	b9401fa1 	ldr	w1, [x29, #28]
  400934:	b9401fa0 	ldr	w0, [x29, #28]
  400938:	1b007c22 	mul	w2, w1, w0
  40093c:	b9401ba0 	ldr	w0, [x29, #24]
  400940:	531f7c01 	lsr	w1, w0, #31
  400944:	0b000020 	add	w0, w1, w0
  400948:	13017c00 	asr	w0, w0, #1
  40094c:	2a0003e1 	mov	w1, w0
  400950:	2a0203e0 	mov	w0, w2
  400954:	97ffffe4 	bl	4008e4 <foo>
  400958:	2a0003e1 	mov	w1, w0
  40095c:	b9402fa0 	ldr	w0, [x29, #44]
  400960:	1b017c00 	mul	w0, w0, w1
  400964:	b9002fa0 	str	w0, [x29, #44]
  400968:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  40096c:	91376000 	add	x0, x0, #0xdd8
  400970:	b9402fa1 	ldr	w1, [x29, #44]
  400974:	97ffff3f 	bl	400670 <printf@plt>
  400978:	b9402fa0 	ldr	w0, [x29, #44]
  40097c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400980:	d65f03c0 	ret

0000000000400984 <inv_arr>:
  400984:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400988:	910003fd 	mov	x29, sp
  40098c:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400990:	91380001 	add	x1, x0, #0xe00
  400994:	910063a0 	add	x0, x29, #0x18
  400998:	a9400c22 	ldp	x2, x3, [x1]
  40099c:	a9000c02 	stp	x2, x3, [x0]
  4009a0:	a9410c22 	ldp	x2, x3, [x1, #16]
  4009a4:	a9010c02 	stp	x2, x3, [x0, #16]
  4009a8:	b9402021 	ldr	w1, [x1, #32]
  4009ac:	b9002001 	str	w1, [x0, #32]
  4009b0:	910063a0 	add	x0, x29, #0x18
  4009b4:	94000008 	bl	4009d4 <arr>
  4009b8:	b94037a1 	ldr	w1, [x29, #52]
  4009bc:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  4009c0:	91376000 	add	x0, x0, #0xdd8
  4009c4:	97ffff2b 	bl	400670 <printf@plt>
  4009c8:	d503201f 	nop
  4009cc:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4009d0:	d65f03c0 	ret

00000000004009d4 <arr>:
  4009d4:	d10043ff 	sub	sp, sp, #0x10
  4009d8:	f90007e0 	str	x0, [sp, #8]
  4009dc:	f94007e0 	ldr	x0, [sp, #8]
  4009e0:	91003000 	add	x0, x0, #0xc
  4009e4:	f90007e0 	str	x0, [sp, #8]
  4009e8:	f94007e0 	ldr	x0, [sp, #8]
  4009ec:	91003000 	add	x0, x0, #0xc
  4009f0:	52800121 	mov	w1, #0x9                   	// #9
  4009f4:	b9000401 	str	w1, [x0, #4]
  4009f8:	d503201f 	nop
  4009fc:	910043ff 	add	sp, sp, #0x10
  400a00:	d65f03c0 	ret

0000000000400a04 <six>:
  400a04:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a08:	910003fd 	mov	x29, sp
  400a0c:	52800060 	mov	w0, #0x3                   	// #3
  400a10:	b9001fa0 	str	w0, [x29, #28]
  400a14:	528000a0 	mov	w0, #0x5                   	// #5
  400a18:	b9001ba0 	str	w0, [x29, #24]
  400a1c:	b9401fa0 	ldr	w0, [x29, #28]
  400a20:	b90017a0 	str	w0, [x29, #20]
  400a24:	b9401ba0 	ldr	w0, [x29, #24]
  400a28:	b90013a0 	str	w0, [x29, #16]
  400a2c:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400a30:	9138a000 	add	x0, x0, #0xe28
  400a34:	b94017a1 	ldr	w1, [x29, #20]
  400a38:	97ffff0e 	bl	400670 <printf@plt>
  400a3c:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400a40:	9138c000 	add	x0, x0, #0xe30
  400a44:	b94013a1 	ldr	w1, [x29, #16]
  400a48:	97ffff0a 	bl	400670 <printf@plt>
  400a4c:	d503201f 	nop
  400a50:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400a54:	d65f03c0 	ret

0000000000400a58 <ser>:
  400a58:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400a5c:	910003fd 	mov	x29, sp
  400a60:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400a64:	91390000 	add	x0, x0, #0xe40
  400a68:	910043a2 	add	x2, x29, #0x10
  400a6c:	aa0003e3 	mov	x3, x0
  400a70:	a9400460 	ldp	x0, x1, [x3]
  400a74:	a9000440 	stp	x0, x1, [x2]
  400a78:	f9400860 	ldr	x0, [x3, #16]
  400a7c:	f9000840 	str	x0, [x2, #16]
  400a80:	910043a0 	add	x0, x29, #0x10
  400a84:	f90017a0 	str	x0, [x29, #40]
  400a88:	f94017a0 	ldr	x0, [x29, #40]
  400a8c:	b9400401 	ldr	w1, [x0, #4]
  400a90:	f94017a0 	ldr	x0, [x29, #40]
  400a94:	b9400802 	ldr	w2, [x0, #8]
  400a98:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400a9c:	9138e000 	add	x0, x0, #0xe38
  400aa0:	97fffef4 	bl	400670 <printf@plt>
  400aa4:	f94017a0 	ldr	x0, [x29, #40]
  400aa8:	91003000 	add	x0, x0, #0xc
  400aac:	f90017a0 	str	x0, [x29, #40]
  400ab0:	f94017a0 	ldr	x0, [x29, #40]
  400ab4:	b9400401 	ldr	w1, [x0, #4]
  400ab8:	f94017a0 	ldr	x0, [x29, #40]
  400abc:	b9400802 	ldr	w2, [x0, #8]
  400ac0:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400ac4:	9138e000 	add	x0, x0, #0xe38
  400ac8:	97fffeea 	bl	400670 <printf@plt>
  400acc:	d503201f 	nop
  400ad0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ad4:	d65f03c0 	ret

0000000000400ad8 <f1>:
  400ad8:	d10043ff 	sub	sp, sp, #0x10
  400adc:	52800140 	mov	w0, #0xa                   	// #10
  400ae0:	b9000fe0 	str	w0, [sp, #12]
  400ae4:	d2800000 	mov	x0, #0x0                   	// #0
  400ae8:	910043ff 	add	sp, sp, #0x10
  400aec:	d65f03c0 	ret

0000000000400af0 <f2>:
  400af0:	d10043ff 	sub	sp, sp, #0x10
  400af4:	f94007e0 	ldr	x0, [sp, #8]
  400af8:	52800141 	mov	w1, #0xa                   	// #10
  400afc:	b9000001 	str	w1, [x0]
  400b00:	f94007e0 	ldr	x0, [sp, #8]
  400b04:	910043ff 	add	sp, sp, #0x10
  400b08:	d65f03c0 	ret

0000000000400b0c <f3>:
  400b0c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400b10:	910003fd 	mov	x29, sp
  400b14:	d2800080 	mov	x0, #0x4                   	// #4
  400b18:	97fffebe 	bl	400610 <malloc@plt>
  400b1c:	f9000fa0 	str	x0, [x29, #24]
  400b20:	f9400fa0 	ldr	x0, [x29, #24]
  400b24:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b28:	d65f03c0 	ret

0000000000400b2c <nine>:
  400b2c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400b30:	910003fd 	mov	x29, sp
  400b34:	52800060 	mov	w0, #0x3                   	// #3
  400b38:	b9001fa0 	str	w0, [x29, #28]
  400b3c:	52800080 	mov	w0, #0x4                   	// #4
  400b40:	b9001ba0 	str	w0, [x29, #24]
  400b44:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400b48:	91396000 	add	x0, x0, #0xe58
  400b4c:	b9401ba3 	ldr	w3, [x29, #24]
  400b50:	b9401fa2 	ldr	w2, [x29, #28]
  400b54:	d2800081 	mov	x1, #0x4                   	// #4
  400b58:	97fffec6 	bl	400670 <printf@plt>
  400b5c:	d503201f 	nop
  400b60:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b64:	d65f03c0 	ret

0000000000400b68 <ten>:
  400b68:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400b6c:	910003fd 	mov	x29, sp
  400b70:	f9000bbf 	str	xzr, [x29, #16]
  400b74:	790033bf 	strh	wzr, [x29, #24]
  400b78:	52800020 	mov	w0, #0x1                   	// #1
  400b7c:	390043a0 	strb	w0, [x29, #16]
  400b80:	52800040 	mov	w0, #0x2                   	// #2
  400b84:	390047a0 	strb	w0, [x29, #17]
  400b88:	52800060 	mov	w0, #0x3                   	// #3
  400b8c:	39004ba0 	strb	w0, [x29, #18]
  400b90:	52800080 	mov	w0, #0x4                   	// #4
  400b94:	39004fa0 	strb	w0, [x29, #19]
  400b98:	528000a0 	mov	w0, #0x5                   	// #5
  400b9c:	390053a0 	strb	w0, [x29, #20]
  400ba0:	528000c0 	mov	w0, #0x6                   	// #6
  400ba4:	390057a0 	strb	w0, [x29, #21]
  400ba8:	52800120 	mov	w0, #0x9                   	// #9
  400bac:	39005ba0 	strb	w0, [x29, #22]
  400bb0:	52800100 	mov	w0, #0x8                   	// #8
  400bb4:	39005fa0 	strb	w0, [x29, #23]
  400bb8:	39405ba0 	ldrb	w0, [x29, #22]
  400bbc:	39007fa0 	strb	w0, [x29, #31]
  400bc0:	39407fa1 	ldrb	w1, [x29, #31]
  400bc4:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400bc8:	91376000 	add	x0, x0, #0xdd8
  400bcc:	97fffea9 	bl	400670 <printf@plt>
  400bd0:	d503201f 	nop
  400bd4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400bd8:	d65f03c0 	ret

0000000000400bdc <elv>:
  400bdc:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400be0:	910003fd 	mov	x29, sp
  400be4:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400be8:	913a6001 	add	x1, x0, #0xe98
  400bec:	910043a0 	add	x0, x29, #0x10
  400bf0:	a9400c22 	ldp	x2, x3, [x1]
  400bf4:	a9000c02 	stp	x2, x3, [x0]
  400bf8:	a9410c22 	ldp	x2, x3, [x1, #16]
  400bfc:	a9010c02 	stp	x2, x3, [x0, #16]
  400c00:	a9420821 	ldp	x1, x2, [x1, #32]
  400c04:	a9020801 	stp	x1, x2, [x0, #32]
  400c08:	910043a0 	add	x0, x29, #0x10
  400c0c:	94000004 	bl	400c1c <ff>
  400c10:	d503201f 	nop
  400c14:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400c18:	d65f03c0 	ret

0000000000400c1c <ff>:
  400c1c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400c20:	910003fd 	mov	x29, sp
  400c24:	f9000fa0 	str	x0, [x29, #24]
  400c28:	f9400fa0 	ldr	x0, [x29, #24]
  400c2c:	91008000 	add	x0, x0, #0x20
  400c30:	f9000fa0 	str	x0, [x29, #24]
  400c34:	f9400fa0 	ldr	x0, [x29, #24]
  400c38:	f85f8000 	ldur	x0, [x0, #-8]
  400c3c:	f90017a0 	str	x0, [x29, #40]
  400c40:	f94017a0 	ldr	x0, [x29, #40]
  400c44:	97fffe83 	bl	400650 <puts@plt>
  400c48:	d503201f 	nop
  400c4c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400c50:	d65f03c0 	ret

0000000000400c54 <counter>:
  400c54:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400c58:	910003fd 	mov	x29, sp
  400c5c:	b9001fa0 	str	w0, [x29, #28]
  400c60:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400c64:	91066000 	add	x0, x0, #0x198
  400c68:	b9400001 	ldr	w1, [x0]
  400c6c:	b9401fa0 	ldr	w0, [x29, #28]
  400c70:	0b000021 	add	w1, w1, w0
  400c74:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400c78:	91066000 	add	x0, x0, #0x198
  400c7c:	b9000001 	str	w1, [x0]
  400c80:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400c84:	91066000 	add	x0, x0, #0x198
  400c88:	b9400001 	ldr	w1, [x0]
  400c8c:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400c90:	91376000 	add	x0, x0, #0xdd8
  400c94:	97fffe77 	bl	400670 <printf@plt>
  400c98:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400c9c:	91066000 	add	x0, x0, #0x198
  400ca0:	b9400000 	ldr	w0, [x0]
  400ca4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400ca8:	d65f03c0 	ret

0000000000400cac <twl>:
  400cac:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400cb0:	910003fd 	mov	x29, sp
  400cb4:	b9001fbf 	str	wzr, [x29, #28]
  400cb8:	14000007 	b	400cd4 <twl+0x28>
  400cbc:	b9401fa0 	ldr	w0, [x29, #28]
  400cc0:	97ffffe5 	bl	400c54 <counter>
  400cc4:	b9001ba0 	str	w0, [x29, #24]
  400cc8:	b9401fa0 	ldr	w0, [x29, #28]
  400ccc:	11000400 	add	w0, w0, #0x1
  400cd0:	b9001fa0 	str	w0, [x29, #28]
  400cd4:	b9401fa0 	ldr	w0, [x29, #28]
  400cd8:	7100141f 	cmp	w0, #0x5
  400cdc:	54ffff0d 	b.le	400cbc <twl+0x10>
  400ce0:	90000000 	adrp	x0, 400000 <_init-0x5b0>
  400ce4:	91376000 	add	x0, x0, #0xdd8
  400ce8:	b9401ba1 	ldr	w1, [x29, #24]
  400cec:	97fffe61 	bl	400670 <printf@plt>
  400cf0:	d503201f 	nop
  400cf4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400cf8:	d65f03c0 	ret

0000000000400cfc <main>:
  400cfc:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400d00:	910003fd 	mov	x29, sp
  400d04:	97ffff99 	bl	400b68 <ten>
  400d08:	97ffffb5 	bl	400bdc <elv>
  400d0c:	97ffffe8 	bl	400cac <twl>
  400d10:	52800000 	mov	w0, #0x0                   	// #0
  400d14:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400d18:	d65f03c0 	ret
  400d1c:	00000000 	.inst	0x00000000 ; undefined

0000000000400d20 <__libc_csu_init>:
  400d20:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d24:	910003fd 	mov	x29, sp
  400d28:	a901d7f4 	stp	x20, x21, [sp, #24]
  400d2c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10138>
  400d30:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10138>
  400d34:	91374294 	add	x20, x20, #0xdd0
  400d38:	913722b5 	add	x21, x21, #0xdc8
  400d3c:	a902dff6 	stp	x22, x23, [sp, #40]
  400d40:	cb150294 	sub	x20, x20, x21
  400d44:	f9001ff8 	str	x24, [sp, #56]
  400d48:	2a0003f6 	mov	w22, w0
  400d4c:	aa0103f7 	mov	x23, x1
  400d50:	9343fe94 	asr	x20, x20, #3
  400d54:	aa0203f8 	mov	x24, x2
  400d58:	97fffe16 	bl	4005b0 <_init>
  400d5c:	b4000194 	cbz	x20, 400d8c <__libc_csu_init+0x6c>
  400d60:	f9000bb3 	str	x19, [x29, #16]
  400d64:	d2800013 	mov	x19, #0x0                   	// #0
  400d68:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400d6c:	aa1803e2 	mov	x2, x24
  400d70:	aa1703e1 	mov	x1, x23
  400d74:	2a1603e0 	mov	w0, w22
  400d78:	91000673 	add	x19, x19, #0x1
  400d7c:	d63f0060 	blr	x3
  400d80:	eb13029f 	cmp	x20, x19
  400d84:	54ffff21 	b.ne	400d68 <__libc_csu_init+0x48>  // b.any
  400d88:	f9400bb3 	ldr	x19, [x29, #16]
  400d8c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400d90:	a942dff6 	ldp	x22, x23, [sp, #40]
  400d94:	f9401ff8 	ldr	x24, [sp, #56]
  400d98:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400d9c:	d65f03c0 	ret

0000000000400da0 <__libc_csu_fini>:
  400da0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400da4 <_fini>:
  400da4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400da8:	910003fd 	mov	x29, sp
  400dac:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400db0:	d65f03c0 	ret
